1. Field of the Invention
The present invention generally relates to a logic signal level converter, and in particular, to an apparatus which converts signals having a logic voltage swing characteristic of ECL (Emitter Coupled Logic) into signals having a logic voltage swing characteristic of MOS level signals used in a MOS circuit.
2. Description of the Related Art
The recent progress in the Bi-CMOS technology permits an ECL circuit comprising bipolar transistors and an MOS circuit comprising MOS transistors to be formed together in the same chip. Normally, the amplitude of the input/output signal of the MOS circuit corresponds to the potential difference between a high and low potential power supplies. The amplitude of the input/output signal of the ECL circuit, however, does not comply with the potential difference between the high and low potential power supplies, but generally corresponds to voltage amplitude smaller than the potential difference. The logic voltage swing of an ECL level signal, therefore, is relatively smaller than that of the MOS level signal. Consequently, a signal level converter or a level converting circuit is required to transfer logic signals between the ECL circuit and MOS circuit.
FIG. 1 shows one type of conventional level converting circuit. NPN transistors Trc1, Trc2 and Trc3 are turned on in response to an enable signal V.sub.CS. When complementary input signals IN1 and IN2 of ECL level are input to the circuit, the collector currents flow through NPN transistors Tr1 and Tr2. The difference between the collector currents flowing in Tr1 and Tr2 is based on the potential difference between the input signals IN1 and IN2. This difference in collector current produces a potential difference between the emitters of the transistors Tr1 and Tr2, and a difference between the amounts of the collector currents of NPN transistors Tr5 and Tr6. The latter difference in collector current, in turn, results in a difference in collector potential between the transistors Tr5 and Tr6.
P channel MOS transistors Tr3 and Tr4 are respectively turned on in response to the ON actions of the associated transistors Tr5 and Tr6, supplying the collector currents to those transistors T5 and Tr6. When the transistors Tr5 and Tr6 are turned on, P channel MOS transistors Tr7 and Tr8 are turned on based on the collector potentials of the transistors Tr5 and Tr6. The difference between the drain currents of the transistors Tr7 and Tr8 is determined by the collector potentials of the transistors Tr5 and Tr6.
In response to the turning on of the transistor Tr7, N channel MOS transistors Tr9 and Tr10 turn on. For example, when the gate potential of the transistor Tr7 rises high and the gate potential of the transistor Tr8 goes low, the gate potential of the transistor Tr10 drops low. Consequently, the transistor Tr8 turns on and the transistor Tr10 nearly turns off. Consequently, the output signal OUT goes high. On the other hand, when the gate potential of the transistor Tr7 falls low and the gate potential of the transistor Tr8 rises high, the gate potential of the transistor Tr10 goes high. As a result, the transistor Tr8 nearly turns off and the transistor Tr10 turns on, setting the output signal OUT low. In this manner, the complements of ECL level signals IN1 and IN2 are converted into a signal having a logic level swing similar to the MOS level output signal OUT.
In this level converting circuit, when a high output signal OUT is produced, the transistor Tr10 does not completely turn off. When the L-level output signal OUT is produced, likewise, the transistor Tr8 does not completely turn off. As a consequence, the amplitude of the output signal OUT does not completely match with the potential difference between the power supply V.sub.CC and ground GND.
Generally speaking, the threshold value of signals used in MOS circuits is determined by the characteristic ratio of the PMOS transistor to the NMOS transistor, both of which are connected in series between the high potential power supply V.sub.CC and the ground GND as the low potential power supply. In many cases, the threshold value is set to around the intermediate potential between the power supply V.sub.CC and the ground GND. In these MOS circuits, when the voltage of the power supply V.sub.CC rises, the threshold value also increases. If the amplitude of the output signal OUT from the level converting circuit is too small when the threshold value of the MOS circuit, coupled to the subsequent stage of the level converting circuit increases, the level converting circuit may inaccurately transmit signals reflective of logic to that MOS circuit.
As the operational speed of the level converting circuit increases in accordance with quick switching of the levels of the input signals IN1 and IN2, the amplitude of the output signal OUT tends to decrease. The faster the level switching of the input signals IN1 and IN2 is, therefore, the more difficult it becomes to accurately transmit actual logic levels to the. MOS circuit.
In the conventional level converting circuit, three stages of bipolar transistors such as the transistors Tr1, Tr5 and Trc3, are present between the power supply V.sub.CC and ground GND. Accordingly, the potential difference between the power supply V.sub.CC and ground GND should be equal to or greater than three times the base-emitter voltage drop V.sub.cs of one bioplar transistor. This inhibits the use of any low voltage power supplies as the high potential power supply V.sub.CC.